? semiconductor components industries, llc, 2012 april, 2012 ? rev. 5 1 publication order number: NB3N106K/d NB3N106K 3.3v differential 1:6 fanout clock driver with hcsl outputs description the NB3N106K is a differential 1:6 clock fanout buffer with high ? speed current steering logic (hcsl) outputs optimized for ultra low propagation delay variation. the NB3N106K is designed with hcsl pci express cl ock distribution and fbdimm applications in mind. inputs can directly accept differential lvpecl, lvds, and hcsl signals per figures 7, 8, and 9. single ? ended lvpecl, hcsl, lvcmos, or lvttl levels are accepted with a proper external v th reference supply per figures 4 and 10. input pins incorporate separate internal 50 termination resistors allowing additional single ended system interconnect flexibility. output drive current is set by connecting a 475 resistor from iref (pin 1) to gnd per figure 6. outputs can also interface to lvds receivers when terminated per figure 11. the NB3N106K specifically guarantees low output?to?output skew. optimal design, layout, and processing minimize skew within a device and from device to device. system designers can take advantage of the NB3N106K?s performance to distribute low skew clocks across the backplane or the motherboard. features ? typical input clock frequency 100, 133, 166, 200, 266, 333, and 400 mhz ? 220 ps typical rise and fall times ? 800 ps typical propagation delay ? tpd 100 ps maximum propagation delay variation per diff pair ? 0.1 ps typical integrated phase jitter rms ? operating range: v cc = 3.0 v to 3.6 v with v ee = 0 v ? typical hcsl output levels (700 mv peak ? to ? peak) ? lvds output levels with interface termination ? these are pb ? free devices* applications ? clock distribution ? pcie, ii, iii ? networking and communications ? high end computing end products ? servers ? fbdimm memory cards ? ethernet switch/routers *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. *for additional marking information, refer to application note and8002/d. qfn ? 24 mn suffix case 485l marking diagram* http://onsemi.com figure 1. simplified logic diagram q0 q0 q1 q1 q4 q4 q5 q5 clk clk v cc gnd r ref iref see detailed ordering and shipping information in the package dimensions section on page 9 of this data sheet. ordering information vtclk vtclk a = assembly location l = wafer lot y = year w = work week = pb ? free package nb3n 106k alyw
NB3N106K http://onsemi.com 2 figure 2. pinout configuration (top view) 1 2 3 4 5 6 789101112 18 17 16 15 14 13 24 23 22 21 20 19 iref vtclk clk clk vtclk gnd vcc q2 q2 q3 q3 vcc vcc q0 q0 q1 q1 vcc vcc q5 q5 q4 q4 vcc NB3N106K exposed pad (ep) table 1. pin description pin name i/o description 1 iref use the iref pin to set the output drive. connect a 475 rref resistor from the iref pin to gnd to produce 2.6 ma of iref current. a current mirror multiplies iref by a factor of 5.4x to force 14 ma through a 50 output load. see figures 6 and 12. 2, 5 vtclk, vtclk ? internal 50 termination resistor connection pins. in the differential configuration when the input termination pins are connected to the common termination voltage, and if no signal is applied then the device may be susceptible to self ? oscillation. 3 clk lvpecl, hcsl, lvds input clock (true) input 4 clk lvpecl, hcsl, lvds input clock (invert) input 8, 10, 14, 16, 20, 22 q[5 ? 0] hcsl or lvds (note 1) output output (invert) (note 1) 9, 11, 15, 17, 21, 23 q[5 ? 0] hcsl or lvds (note 1) output output (true) (note 1) 6 gnd ? supply ground. gnd pin must be externally connected to power supply to guarantee proper operation. 7, 12, 13, 18, 19, 24 v cc ? positive voltage supply pin. v cc pin must be externally connected to a power supply to guarantee proper operation. exposed pad ep gnd exposed pad. the thermally exposed pad (ep) on package bottom (see case drawing) must be attached to a sufficient heat ? sinking conduit for proper thermal operation and electrically connected to the circuit board ground (gnd). 1. outputs can also interface to lvds receiver when terminated per figure 11.
NB3N106K http://onsemi.com 3 table 2. attributes characteristic value esd protection human body model machine model >2 kv 200 v moisture sensitivity (note 2) qfn ? 24 level 1 flammability rating oxygen index: 28 to 34 ul 94 v ? 0 @ 0.125 in transistor count 286 meets or exceeds jedec spec eia/jesd78 ic latchup test 2. for additional information, see application note and8003/d. table 3. maximum ratings (note 3) symbol parameter condition 1 condition 2 rating unit v cc positive power supply gnd = 0 v 4.6 v v i positive input gnd = 0 v gnd ? 0.3 v i v cc v i out output current continuous surge 50 100 ma ma t a operating temperature range qfn ? 24 ? 40 to +85 c t stg storage temperature range ? 65 to +150 c ja thermal resistance (junction ? to ? ambient) (note 3) 0 lfpm 500 lfpm qfn ? 24 qfn ? 24 37 32 c/w c/w jc thermal resistance (junction ? to ? case) 2s2p (note 3) qfn ? 24 11 c/w t sol wave solder pb ? free 265 c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 3. jedec standard 51 ? 6, multilayer board ? 2s2p (2 signal, 2 power) with 8 filled thermal vias under exposed pad..
NB3N106K http://onsemi.com 4 table 4. dc characteristics (v cc = 3.0 v to 3.6 v, t a = ? 40 c to +85 c note 4) symbol characteristic min typ max unit i gnd gnd supply current (all outputs loaded) 60 90 ma i cc power supply current (all outputs loaded) 210 260 ma i ih input high current 2.0 150 a i il input low current ? 150 ? 2.0 a r tin internal input termination resistor 45 50 55 differential input driven single ? ended v th input threshold reference voltage range (note 5) 350 v cc ? 1000 mv v ih single ended input high voltage v th + 150 v cc mv v il single ended input low voltage gnd v th ? 150 mv differential inputs driven differentially (figures 7, 8 and 9) v ihd differential input high voltage 425 v cc ? 850 mv v ild differential input low voltage gnd v cc ? 1000 mv v id differential input voltage (v ihd v ild ) 150 v cc ? 850 mv v cmr input common mode range 350 v cc ? 1000 mv hcsl outputs (figure 4) v oh output high voltage 600 740 900 mv v ol output low voltage ? 150 0 150 mv note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 4. measurements taken with with outputs loaded 50 to gnd. connect a 475 resistor from iref (pin 1) to gnd. see figure 6. 5. v th is applied to the complementary input when operating in single ended mode per figure 4.
NB3N106K http://onsemi.com 5 table 5. ac characteristics v cc = 3.0 v to 3.6 v, gnd = 0 v; ? 40 c to +85 c (note 6) symbol characteristic min typ max unit v outpp output voltage amplitude (@ v inppmin ) f in 400 mhz 725 1000 mv t plh , t phl propagation delay (see figure 3a) clk/clk to qx/qx 550 800 1100 ps t plh , t phl propagation delay variation per each diff pair (note 7) (see figure 3a) clk/clk to qx/qx 100 ps t skew duty cycle skew (note 8) within -device skew device to device skew (note 9) 20 100 150 ps t jit integrated phase jitter rms (note 10) 0.1 ps v inpp input voltage swing/sensitivity (differential configuration) 0.150 v cc ? 0.85 v v cross absolute crossing magnitude voltage (see figure 3b) 250 550 mv v cross variation in magnitude of v cross (see figure 3b) 150 mv t r , t f absolute magnitude in output risetime and falltime (from 175 mv to 525 mv) (see figure 3b) qx, qx 150 220 400 ps tr, tf variation in magnitude of risetime and falltime (single ? ended) at v cc = 3.0 v, 3.3 v, 3.6 v (see figure 3b) qx, qx 125 ps note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 6. measured by forcing v inpp (min) from a 50% duty cycle clock source. measurements taken all outputs loaded 50 to gnd per figure 6. connect a 475 resistor from iref (pin 1) to gnd. see figure 6. 7. measured from the input pair crosspoint to each single output pair crosspoint across temp and voltage ranges per figure 3. 8. duty cycle skew is measured between differential outputs using the deviations of the sum of t pw- and t pw+ . 9. skew is measured between outputs under identical transition conditions @ 50 mhz. 10. phase noise integrated from 12 khz to 20 mhz.
NB3N106K http://onsemi.com 6 figure 3. ac reference measurement clk clk q q t p lh t p hl v inpp = v ih (clk) ? v il (clk) = v ih (clk ) ? v il (clk ) v outpp = v oh (q x ) ? v ol (q x ) = v oh (q x ) ? v ol (q x ) t p lh t p hl t r t f 525 mv 175 mv 525 mv 175 mv v cross v cross tr max ? tr min = t r tr min tf max ? tf min = t f tf min tf max tr max (a) propagation delay and propagation delay variation (b) tr, tf and tr, tf (c) vcross and vcross q x q x q x q x q x q x figure 4. single ? ended interconnect v th reference voltage clk v th clk v th v cc v ee v cmrmin v cmrmax v cmr in in v ihdmax v ildmax v id = v ihd ? v ild v ihdtyp v ildtyp v ihdmin v ildmin figure 5. v th diagram
NB3N106K http://onsemi.com 7 figure 6. typical termination configuration for output driver and device evaluation a . connect 475 resistor rref from iref pin to gnd. b . r s1 , r s2 : 0 for test and evaluation. select to minimizing ringing. c . c l1 , c l2 : receiver input simulation (for test only not added to application circuit. d . d l1 , d l2 termination and load resistors located at received inputs. c l1 c 2 pf c l2 c 2 pf z 0 = 50 z 0 = 50 receiver r s1 b r s2 b hcsl driver r ref a r l1 d 50 r l2 d 50 qx qx iref 50 v tclk = v tclk = v cc ? 2.0 v lvpecl driver z 0 = 50 z 0 = 50 v cc = 3.3 v / 2.5 v v cc = 3.3 v gnd gnd 50 v tclk v tclk figure 7. lvpecl interface *rtin, internal input termination resistor 50 v tclk = v tclk lvds driver z 0 = 50 z 0 = 50 v cc = 3.3 v / 2.5 v / 1.8 v v cc = 3.3 v gnd gnd 50 v tclk v tclk figure 8. lvds interface *rtin, internal input termination resistor NB3N106K NB3N106K clk clk clk clk
NB3N106K http://onsemi.com 8 50 v tclk = v tclk = gnd hcsl driver z 0 = 50 z 0 = 50 v cc = 3.3 v / 2.5 v / 1.8 v v cc gnd gnd 50 v tclk v tclk figure 9. standard 50 load hcsl interface *rtin, internal input termination resistor NB3N106K gnd 50 v tclk = open lvcmos/ lvttl driver z 0 = 50 v cc = 3.3 v / 2.5 v / 1.8 v v cc gnd gnd 50 v tclk v tclk *rtin, internal input termination resistor NB3N106K figure 10. lvcmos/lvttl interface clk = v th v th v tclk = open clk clk clk clk figure 11. hcsl interface termination to lvds hcsl device lvds device qx qx z o = 50 z o = 50 r l = 150 r l = 150 100 100 gnd r ref iref NB3N106K figure 12. hcsl simplified output structure r ref r l1 r l2 qx qx iref 2.6 ma 475 50 50 14 ma
NB3N106K http://onsemi.com 9 ordering information device package shipping ? NB3N106Kmng qfn24 (pb ? free) 92 units / rail NB3N106Kmnr2g qfn24 (pb ? free) 3000 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
NB3N106K http://onsemi.com 10 package dimensions qfn24, 4x4, 0.5p case 485l ? 01 issue a notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b applies to plated terminal and is measured between 0.25 and 0.30 mm from terminal. 4. coplanarity applies to the exposed pad as well as the terminals. seating plane d b 0.15 c a2 a a3 a e pin 1 identification 2x 0.15 c 2x 0.08 c 0.10 c a1 c dim min max millimeters a 0.80 1.00 a1 0.00 0.05 a2 0.60 0.80 a3 0.20 ref b 0.20 0.30 d 4.00 bsc d2 2.70 2.90 e 4.00 bsc e2 2.70 2.90 e 0.50 bsc l 0.30 0.50 24x l d2 b 1 6 7 18 13 19 e 12 e2 e 24 0.10 b 0.05 a c c ref on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. sc illc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems in tended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scill c and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising ou t of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding th e design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resa le in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 NB3N106K/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loca l sales representative
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